Abstract— The increasing demand for energy-efficient and high-performance analog-to-digital converters (ADCs) in modern wireless communication systems necessitates the development of architectures that balance speed, accuracy, and power consumption. This work addresses the challenge by designing and verifying a synchronous Successive Approximation Register (SAR) ADC optimized for low-power mixed-signal applications using 45nm CMOS technology. The proposed ADC adopts a fully dynamic architecture to eliminate static power dissipation, making it highly suitable for energy-constrained environments. Key architectural components include a precision clock phase generator for accurate timing control, a capacitive Digital-to-Analog Converter (CAPDAC) for power-efficient signal conversion, and a StrongArm dynamic comparator for fast and robust decision-making. The design achieves a resolution of 10 bits with a high Effective Number of Bits (ENOB) of 9.86 bits and SINAD of 61.12 dB at 100 MS/s sampling rate, while consuming only 2.63 µW. To ensure functional correctness and performance reliability, a modular “divide-and-conquer” verification strategy is implemented. Each subsystem, including the comparator, DAC, and clock generator, is analyzed independently to identify and quantify sources of noise and error. Advanced simulation tools such as Virtuoso ADE and Cadence Spectre APS are employed, complemented by pnoise and transient noise analysis techniques. Low Discrepancy Sampling (LDS)-based Monte Carlo simulations are conducted to evaluate design robustness across process-voltage-temperature (PVT) variations. The final outcome verifies the viability of the proposed design for integration into modern system-on-chip (SoC) platforms. The combination of a dynamic, low-power architecture and structured verification methodology contributes to the advancement of energy-efficient, high-precision SAR ADCs for embedded systems.