Abstract— Electronic warfare systems have stringent requirements of ultra-low phase noise and substantial high-power oscillators, thus demanding an additional amplifier to drive subsequent stages. Most of the oscillator designs – realized using GaAs/SiGe technology – have the advantage of low phase noise profile, but offer low output power. GaN-based Dielectric Resonator Oscillators (DRO) could be one of the solutions due to their high power, quality factor, and compact size. Their phase noise profile can be further improved by Phase Locking loops (PLL). In this work, a hybrid phase-locking technique that amalgamates the salient features of the two most common techniques available in the literature, namely Analog PLL and Digital PLL, is presented. The designed GaN-based PL-DRO presents a substantial output power of 24 dBm at 12 GHz with excellent phase noise of -119 dBc/Hz at 100 kHz offset frequency. Performance evaluation of the proposed design compared with the state-of-the-art similar designs reported in literature has been carried out. It reveals that the proposed design is the most compact, low-cost, and efficient. Therefore, the suggested phase-locking approach can be used to design ultra-low phase noise DROs for strategic electronics communication systems.