Abstract— Numerous ECG denoising systems have been developed, yet many lack real-time capability and require substantial hardware and power due to the computational complexity of their underlying algorithms. The adaptive dual threshold filter (ADTF) is a recent method that has demonstrated strong denoising performance, and this paper introduces a low-power, low-hardware embedded architecture that enables real-time, high-quality ECG filtering at low processing frequencies. The proposed pipelined FPGA-based design leverages ADTF’s low complexity through a non-structural implementation that significantly reduces resource usage; input data are optimized via compact unsigned binary representation to support efficient fixed-point processing; and maximum/minimum calculations are accelerated through parallel multiplexers and registers, allowing operation at only 1.44 kHz—four times the ECG acquisition rate. Denoising performance is assessed using PRD and SNR improvement, while architectural efficiency is evaluated through power, resource, and timing benchmarks, all showing substantial gains over existing ADTF architectures and other state-of-the-art systems. Overall, the results demonstrate that ADTF, combined with the proposed architecture, offers an effective, low-complexity solution for real-time ECG noise reduction and represents a suitable low-power hardware option for continuous ECG monitoring applications.