Abstract— With rapid technology scaling, Flip Flops have become more susceptible to metastability errors due to higher clock frequency and the well-known effects of process, temperature, and voltage fluctuations that can result in persistent setup and hold time violations. However, it is accepted that scaling cannot continue indefinitely; and approaches involving new materials and device structures have to be devised to circumvent the unavoidable barriers due to the reduction in device dimensions. A potential candidate to meet the criteria of low static power dissipation while maintaining high-speed operation is multiple gate MOSFETs (MuGFETs). This is due to its high current drive capability attained through its superior gate control over the channel and excellent suppression of short-channels. In this paper, the influence of key design parameters of multiple gate MOSFETs on the metastability robustness of Power PC Flip Flops is investigated. It was found that the resolution time constant (τ) can be reduced by increasing the effective width of the devices to enhance the device transconductance. For instance, this can be done by increasing the number of fins and fingers as well as fin widths of the devices. Furthermore, the impact of technology scaling on the metastability behavior of Flip Flops is considered. It is shown that using smaller technology nodes provides better metastability resilience.